Low Noise Amplifier for Neural Interfaces

Designed and simulated a low noise sub-threshold amplifier for brain interfacing electronics

Cadence VirtuosoPSpice

Overview

Developed a low noise amplifier for reading electrical impulses generated by the brain in collaboration with the Morizio Lab at Duke University

Problem / Motivation

Neural impulses in the brain are very low power signals, not readable by most electronics. In order for those signals to be interpeted by a machine, they need to be amplified to a higher signal level. This amplification is also required to be really low power usage for implantable devices where longevity and reliability are the most important factors.

Technical Design

To develop this solution, we used industry standard PDKs and the Cadence Virtuoso suite in order to design, simulate, and layout the amplifiers. Using ultra low threshold MOSFETs, I designed a multi-stage operational transconductance amplifer (OTA) that could amplify the signal 100x while keeping within the bandwidth of brain signals and maintaining an excellent signal to noise ratio. These designs were all simulated in Virtuoso to validate the design and then laid out. Post layout, we confirmed that the layout introduced minimal parasitics, keeping us within spec.

Key Challenges

Maintain power efficiency required for implantable devices
Operating below the transistor threshold added complexity to simulations

Results